DS823 Datasheet, PDF (16/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Table 5: Sink Static Configuration Parameter Definition (Cont’d)
Name
Range
Description
RSClkPhase
Sink Status Clock Phase. Determines whether the FIFO
Status Channel data (RStat[1:0]) changes on the rising edge
n/a
of RSClk or the falling edge of RSClk:
0: RSClkPhase = rising edge of RSClk (default value)
1: RSClkPhase = falling edge of RSClk
FifoAFMode[1:0]
Sink Almost Full Mode. Selects the mode of operation for the
Sink interface when the Sink core reaches the Almost Full
threshold (SnkAFThresAssert).
If FifoAFMode is set to “00,” the Sink interface goes out-of-
frame when the core is almost full, and the Sink Status logic
sends the framing sequence “11” until Sink core is not almost
full.
n/a
If FifoAFMode is set to “01,” the Sink interface remains in
frame (SnkOof deasserted), and the Sink Status logic sends
satisfied “10” on all channels until SNKFF_ALMOSTFULL_N
is deasserted.
If FifoAFMode is set to “10” or “11,” the Sink interface will
remain in frame (SnkOof deasserted), and the Sink Status
logic continues to drive out the user’s status information (i.e.,
continues in normal operation). In this case, the user should
take immediate action to prevent overflow and loss of data.
16
www.xilinx.com
DS823 July 25, 2012
Product Specification