DS823 Datasheet, PDF (22/33 Pages) Xilinx, Inc – DIP-4 and DIP-2 parity generation and verification

LogiCORE IP SPI-4.2 v12.2
Source AXI4-Lite Control Interface
The Source AXI4-Lite Control interface is used to program the calendar memory, read status memory,
and program static configuration memory. This memory space is defined in Figure 5.
The calendar determines the status channel order and frequency. Through this interface, the user can
program the calendar buffer to determine the order and frequency with which channel status is sent on
the SPI-4.2 interface.
Flow control data from the SPI-4.2 Status interface can be received by the user in one of two ways:
• Addressable Mode (AXI4-Lite Control Interface): In this mode, the Status information is stored in
the Axi4-Lite Control memory space and can be retrieved at the user’s convenience.
• Transparent Mode (AXI4-Stream Status Interface): In this mode, the Status information is
provided real-time as it is received on TStat and is not stored within the core. This means the
status memory space is defined in Figure 5 is not usable (“Reserved”) in this mode and reads to it
will return all zeroes.
The static configuration memory enables customization of the core based on individual system
requirements. These settings are statically driven inside the core by writing registers through the
Control interface. Table 9 defines the Control interface signals, and Table 11 defines the static
configuration parameters.
Table 9: Source AXI4-Lite Control interface Signals
Name
AXI_SRC_ACLK
AXI_SRC_ARESETN
AXI_SRC_ARREADY
AXI_SRC_ARVALID
AXI_SRC_ARADDR[9:0]
Direction Clock Domain
Description
Input
N/A
AXI4-Lite Interface Clock. All Sink AXI4-Lite signals
are synchronous to the rising edge of this clock.
Input
AXI4-Lite Interface Reset. Active-low signal that
enables the user to reset the AXI4-Lite interface and
all associated logic and memories to chosen CORE
AXI_SRC_ACLK
Generator settings. The reset signal can be asserted
asynchronously, but deassertion must be
synchronous after the rising edge of ACLK. See the
AMBA AXI4 Protocol specification for more
information.
Read Address Channel
Output
AXI4-Lite Read Address Core Handshake.
Indicates the core is ready to accept a read address.
AXI_SRC_ACLK
When both ARREADY and ARVALID are asserted on
a clock cycle, a one-word read request occurs for the
address provided on ARADDR and the core fetches
the contents of that address.
Input
AXI4-Lite Read Address User Handshake.
Indicates the user is presenting a valid read address.
AXI_SRC_ACLK
When both ARREADY and ARVALID are asserted on
a clock cycle, a one-word read request occurs for the
address provided on ARADDR and the core fetches
the contents of that address.
Input
AXI_SRC_ACLK
AXI4-Lite Read Address. Address to be read by the
user application.
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DS823 July 25, 2012
Product Specification