DS692 Datasheet, PDF (9/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
GTX_DUAL Tile Switching Characteristics
Consult UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 17: GTX_DUAL Tile Performance
Symbol
Description
F_GTXMAX
F_GPLLMAX
F_GPLLMIN
Maximum GTX transceiver data rate
Maximum PLL frequency
Minimum PLL frequency
Value
4.25
3.25
1.48
Units
Gb/s
GHz
GHz
Table 18: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Symbol
Description
Value
F_GTXDRPCLK GTX DCLK (DRP clock) maximum frequency
150
Units
MHz
Table 19: GTX_DUAL Tile Reference Clock Switching Characteristics
Symbol
F_GCLK
T_RCLK
T_FCLK
T_DCREF
T_GJTT
Description
Reference clock frequency range⁽¹⁾
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Reference clock total jitter⁽²⁾⁽³⁾
Conditions
CLK
20% – 80%
80% – 20%
CLK
At 100 KHz
At 1 MHz
T_LOCK Clock recovery frequency acquisition time
T_PHASE Clock recovery phase acquisition time
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
Min Typ
60
–
–
200
–
200
40
50
–– –145
–
–150
–
0.25
–
–
Max
Units
650
MHz
–
ps
–
ps
60
%
–
dBc/Hz
–
dBc/Hz
1
ms
200
µs
Notes:
1. GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
2. GTX_DUAL jitter characteristics measured using a clock with specification T_GJTT. A reference clock with higher phase noise can be used
with link margin trade off.
3. The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see Table 21 and Table 22.
X-Ref Target - Figure 5
80%
T_RCLK
20%
T_FCLK
DS692_05_031510
Figure 5: Reference Clock Timing Parameters
DS692 (v1.3.1) January 16, 2015
Product Specification
www.xilinx.com
Send Feedback
9