DS692 Datasheet, PDF (38/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Virtex-5QV Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 61. Values are expressed in nanoseconds unless otherwise noted.
Table 61: Global Clock Setup and Hold without DCM or PLL
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSFD/ T_PHFD
Full Delay (Legacy Delay or Default Delay) XQR5VFX130
Global Clock and IFF⁽²⁾ without DCM or PLL
Value
3.59/0.81
Units
ns
Notes:
1. Setup and Hold times are measured over worst-case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch.
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Table 62: Global Clock Setup and Hold with DCM in System-Synchronous Mode
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSDCM/T_PHDCM
No Delay Global Clock and IFF⁽²⁾ with DCM in XQR5VFX130
System-Synchronous Mode
Value
3.84/0.76
Units
ns
Notes:
1. Setup and Hold times are measured over worst-case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 63: Global Clock Setup and Hold with DCM in Source-Synchronous Mode
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSDCM0/T_PHDCM0
No Delay Global Clock and IFF⁽²⁾ with DCM in XQR5VFX130
Source-Synchronous Mode
Value
1.62/2.43
Units
ns
Notes:
1. Setup and Hold times are measured over worst-case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 64: Global Clock Setup and Hold with PLL in System-Synchronous Mode
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSPLL/T_PHPLL
No Delay Global Clock and IFF⁽²⁾ with PLL in XQR5VFX130
System-Synchronous Mode
Value
3.83/0.58
Units
ns
Notes:
1. Setup and Hold times are measured over worst-case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS692 (v1.3.1) January 16, 2015
Product Specification
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