DS692 Datasheet, PDF (40/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5QV FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 68: Duty Cycle Distortion and Clock-Tree Skew
Symbol
T_{DCD_CLK}
T_CKSKEW
T_{DCD_BUFIO}
T_BUFIOSKEW
T_{DCD_BUFR}
Description
Global clock tree duty cycle distortion⁽¹⁾
Global clock tree skew⁽²⁾
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock region
Regional clock tree duty cycle distortion
Device
XQR5VFX130
XQR5VFX130
XQR5VFX130
XQR5VFX130
XQR5VFX130
Value
0.12
1.91
0.10
0.08
0.25
Units
ns
ns
ns
ns
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T_CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 69: Package Skew
Symbol
T_PKGSKEW
Description
Package Skew⁽¹⁾
Device
XQR5VFX130
Package
CF1752
Value
140.94
Units
ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 70: Sample Window
Symbol
T_SAMP
T_{SAMP_BUFIO}
Description
Sampling Error at Receiver Pins⁽¹⁾
Sampling Error at Receiver Pins using BUFIO⁽²⁾
Device
XQR5VFX130
XQR5VFX130
Value
0.62
0.51
Units
ns
ns
Notes:
1. This parameter indicates the total sampling error of Virtex-5QV FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-5QV FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 71: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T_PSCS/T_PHCS
Setup/Hold of I/O clock
Pin-to-Pin Clock-to-Out Using BUFIO
T_ICKOFCS
Clock-to-Out of I/O clock
Value
–0.26/2.13
6.03
Units
ns
ns
DS692 (v1.3.1) January 16, 2015
Product Specification
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