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DS692 Datasheet, PDF (18/41 Pages) Xilinx, Inc – Radiation-Hardened
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Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay.
Table 30: Input Delay Measurement Methodology
Description
I/O Standard Attribute
LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL
VL (1)(2)
0
VH (1)(2)
3.0
VMEAS(1)(3)(5) VREF(1)(4)(5)
1.4
–
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
0
3.3
1.65
–
LVCMOS, 2.5V
LVCMOS25
0
2.5
1.25
–
LVCMOS, 1.8V
LVCMOS18
0
1.8
0.9
–
LVCMOS, 1.5V
LVCMOS15
0
1.5
0.75
–
PCI (Peripheral Component Interconnect),
33 MHz, 3.3V
PCI33_3
Per PCI™ Specification
–
PCI, 66 MHz, 3.3V
PCI66_3
Per PCI Specification
–
PCI-X, 133 MHz, 3.3V
PCIX
Per PCI-X™ Specification
–
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic),
Class I and II
GTL
GTLP
HSTL_I, HSTL_II
VREF – 0.2
VREF – 0.2
VREF – 0.5
VREF + 0.2
VREF + 0.2
VREF + 0.5
VREF
VREF
VREF
0.80
1.0
0.75
HSTL, Class III and IV
HSTL, Class I and II, 1.8V
HSTL, Class III and IV, 1.8V
HSTL_III, HSTL_IV
HSTL_I_18, HSTL_II_18
HSTL_III_18,
HSTL_IV_18
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF
VREF
VREF
0.90
0.90
1.08
SSTL (Stub Terminated Transceiver Logic),
SSTL3_I, SSTL3_II
VREF – 1.00 VREF + 1.00
VREF
1.5
Class I and II, 3.3V
SSTL, Class I and II, 2.5V
SSTL, Class I and II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
AGP
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
LDT (HyperTransport), 2.5V
LVDS_25
LVDSEXT_25
LDT_25
VREF – 0.75
VREF – 0.5
VREF –
(0.2 xVCCO)
1.2 – 0.125
VREF + 0.75
VREF + 0.5
VREF +
(0.2 xVCCO)
1.2 + 0.125
1.2 – 0.125 1.2 + 0.125
0.6 – 0.125 0.6 + 0.125
VREF
VREF
VREF
0(6)
0(6)
0(6)
1.25
0.90
AGP Spec
–
–
–
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Input voltage level from which measurement starts.
4. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6.
6. The value given is the differential input voltage.
DS692 (v1.3.1) January 16, 2015
Product Specification
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