DS692 Datasheet, PDF (31/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
PLL Switching Characteristics
PLL in PMCD mode is not supported for operation beyond the industrial temperature range.
Table 46: PLL Specification
F_INMAX
F_INMIN
Symbol
F_INJITTER
F_INDUTY
F_VCOMIN
F_VCOMAX
F_BANDWIDTH
T_STAPHAOFFSET
T_OUTJITTER
T_OUTDUTY
T_LOCKMAX
F_OUTMAX
F_OUTMIN
T_EXTFDVAR
RST_MINPULSE
F_PFDMAX
F_PFDMIN
T_FBDELAY
Description
Value
Units
Maximum Input Clock Frequency
516
MHz
Minimum Input Clock Frequency
19
MHz
Maximum Input Clock Period Jitter
<20% of clock input period or 1 ns
Max
Allowable Input Duty Cycle: 19-49 MHz
25
%
Allowable Input Duty Cycle: 50-199 MHz
30
%
Allowable Input Duty Cycle:
200-399 MHz
35
%
Allowable Input Duty Cycle:
400-499 MHz
40
%
Allowable Input Duty Cycle: >500 MHz
45
%
Minimum PLL VCO Frequency
400
MHz
Maximum PLL VCO Frequency
800
MHz
Low PLL Bandwidth at Typical
1
MHz
High PLL Bandwidth at Typical
4
MHz
Static Phase Offset of the PLL Outputs
120
ps
PLL Output Jitter
Note 1
PLL Output Clock Duty Cycle
Precision⁽²⁾
PLL Maximum Lock Time⁽³⁾
200
ps
100
µs
PLL Maximum Output Frequency
PLL Minimum Output Frequency⁽⁴⁾
360
MHz
3.13
MHz
External Clock Feedback Variation
< 20% of clock input period or
1 ns Max
Minimum Reset Pulse Width
5
ns
Maximum Frequency at the Phase
Frequency Detector
360
MHz
Minimum Frequency at the Phase
Frequency Detector
19
MHz
Maximum External Delay in the
Feedback Path
3 ns Max or one CLKIN cycle
Notes:
1. Values for this parameter are available in the Architecture Wizard.
2. Includes global clock buffer.
3. The LOCK signal must be sampled after T_LOCKMAX. The LOCK signal is invalid after configuration or reset until the T_LOCKMAX time has
expired.
4. Calculated as F_VCO/128 assuming output duty cycle is 50%.
DS692 (v1.3.1) January 16, 2015
Product Specification
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