DS692 Datasheet, PDF (27/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 41: DSP48E Switching Characteristics (Cont’d)
Symbol
Description
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_M
{ACIN, BCIN} input to {P, CARRYOUT} output using
multiplier
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_NM
{ACIN, BCIN} input to {P, CARRYOUT} output not
using multiplier
TDSPDO_{ACINACOUT, BCINBCOUT}
{ACIN, BCIN} input to {ACOUT, BCOUT} output
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_M
{ACIN, BCIN} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_NM
{ACIN, BCIN} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output not using multiplier
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP,
{PCIN, CARRYCASCIN, MULTSIGNIN} input to {P,
PCINCRYOUT, CRYCINCRYOUT, MULTSIGNINCRYOUT} CARRYOUT} output
TDSPDO_{PCINPCOUT, CRYCINPCOUT,
MULTSIGNINPCOUT, PCINCRYCOUT,
CRYCINCRYCOUT, MULTSIGNINCRYCOUT,
PCINMULTSIGNOUT, CRYCINMULTSIGNOUT,
MULTSIGNINMULTSIGNOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN} input to
{PCOUT, CARRYCASCOUT, MULTSIGNOUT}
output
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP}
CLK (PREG) to {P, CARRYOUT} output
TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP}
CLK (PREG) to {CARRYCASCOUT, PCOUT,
MULTSIGNOUT} output
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM}
CLK (MREG) to {P, CARRYOUT} output
TDSPCKO_{PCOUTM, CRYCOUTM, MULTSIGNOUTM} CLK (MREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M
CLK (AREG, BREG) to {P, CARRYOUT} output using
multiplier
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM
CLK (AREG, BREG) to {P, CARRYOUT} output not
using multiplier
TDSPCKO_{PC, CRYOUTC}
CLK (CREG) to {P, CARRYOUT} output
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB}
CLK (AREG, BREG) to {ACOUT, BCOUT}
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M
CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM
CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output not using multiplier
TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (CREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
Maximum Frequency
F_MAX
F_{MAX_PATDET}
F_{MAX_MULT_NOMREG}
F_{MAX_MULT_NOMREG_PATDET}
With all registers used
With pattern detector
Two register multiply without MREG
Two register multiply without MREG with pattern
detect
Value
4.30
2.49
1.46
4.30
2.71
2.04
2.26
0.63
0.69
2.76
2.98
4.73
2.94
2.93
0.88
4.73
3.16
3.15
360.00
328.00
220.00
203.20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
DS692 (v1.3.1) January 16, 2015
Product Specification
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