DS692 Datasheet, PDF (26/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
DSP48E Switching Characteristics
Table 41: DSP48E Switching Characteristics
Symbol
Description
Value Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
{A, B, ACIN, BCIN} input to {A, B} register CLK
0.29/0.34 ns
TDSPDCK_CC/TDSPCKD_CC
C input to C register CLK
0.23/0.42 ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to M register CLK
1.91/0.19 ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
{A, B, ACIN, BCIN} input to P register CLK using
multiplier
3.64/–0.30 ns
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
{A, B, ACIN, BCIN} input to P register CLK not using 2.05/–0.10 ns
multiplier
TDSPDCK_CP/TDSPCKD_CP
C input to P register CLK
1.91/–0.13 ns
TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
{PCIN, CARRYCASCIN, MULTSIGNIN} input to
P register CLK
1.46/0.11 ns
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
{CEA1, CEA2A, CEB1B, CEB2B} input to {A, B}
register CLK
0.37/0.34 ns
TDSPCCK_CECC/TDSPCKC_CECC
CEC input to C register CLK
0.29/0.31 ns
TDSPCCK_CEMM/TDSPCKC_CEMM
CEM input to M register CLK
0.40/0.29 ns
TDSPCCK_CEPP/TDSPCKC_CEPP
CEP input to P register CLK
0.82/0.01 ns
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/
TDSPCKC_{RSTAA, RSTBB}
{RSTA, RSTB} input to {A, B} register CLK
0.37/0.34 ns
TDSPCCK_RSTCC/ TDSPCKC_RSTCC
RSTC input to C register CLK
0.29/0.31 ns
TDSPCCK_RSTMM/ TDSPCKC_RSTMM
RSTM input to M register CLK
0.40/0.29 ns
TDSPCCK_RSTPP/TDSPCKC_RSTPP
RSTP input to P register CLK
0.82/0.01 ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M
{A, B} input to {P, CARRYOUT} output using multiplier 4.30
ns
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM
{A, B} input to {P, CARRYOUT} output not using
multiplier
2.49
ns
TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT}
{C, CARRYIN} input to {P, CARRYOUT} output
2.33
ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT}
{A, B} input to
{ACOUT, BCOUT} output
1.46
ns
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M
{A, B} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
4.30
ns
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM
{A, B} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output not using multiplier
2.71
ns
TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT,
{C, CARRYIN} input to {PCOUT, CARRYCASCOUT,
2.55
ns
CRYINPCOUT, CRYINCRYCOUT,
MULTSIGNOUT} output
CRYINMULTSIGNOUT}
DS692 (v1.3.1) January 16, 2015
Product Specification
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