DS692 Datasheet, PDF (41/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
07/19/2010
08/23/2010
07/12/2011
07/24/2013
01/13/2015
01/16/2015
Version
1.0
1.0.1
1.1
1.2
1.3
1.3.1
Revision
Initial Xilinx release.
Released to www.xilinx.com.
Moved data sheet from Advance Product Specification to Production. This includes revising Table 26 and
updating Note 1 in Table 27.
Updated values and notes in Table 2 (I_IN) and Table 3 (maximum I_REF , I_L , I_RPU, and I_BATT), Table 4,
Table 5, Table 7 (V_IH minimum for PCI standards), Table 8 (V_OD maximum), and V_OCM in Table 9 and
Table 10.
Completely updated Table 5 and the Power-On Power Supply Requirements section including adding a
required power-down sequence.
Removed Table 11: LVPECL DC Specifications as the LVPECL standard is not supported in this data sheet.
Removed LVPECL standard from Table 28, Table 30, and Table 31.
Updated the values and notes in Table 13 through Table 18, and Table 19 through Table 23. Removed
Table 25: Register-to-Register Performance. Added values and note 3 to Table 37. Added F_{MAX_WRITEBACK}
value in Table 40 and removed note 11.
In Table 42, updated values for T_PL, T_POR, T_ICCK, T_SMCKCSO, T_SMDCCK/T_SMCCKD, T_SMCSCCK/T_SMCCKCS,
T_SMCCKW/T_SMWCCK, T_TAPTCK, T_TCKTAP, T_MCCKL, and T_MCCKH, and added F_RBCCK.
Revised description of PLL support in PLL Switching Characteristics, page 31 and removed Table 49: PLL
in PMCD Mode Switching Characteristics.
Revised description of DCM support in DCM Switching Characteristics, page 32 and removed Table 51:
Operating Frequency Ranges for DCM in Maximum Range (MR) Mode.
In Table 51, removed T_{RANGE_MR}, T_{TAP_MR_MIN}, and T_{TAP_MR_MAX}. Added value to Table 69. Updated the
Notice of Disclaimer.
Replaced XPOWER with Xilinx Power throughout. In Important Note, removed “commercial” from second
sentence and removed sentence describing differentiation in quiescent supply current by speed grade.
Updated Note 3 and added Note 4 to Table 4. Updated title of Table 5. Updated Note 4 in Table 13. Updated
Note 3 in Table 14. In Table 18, replaced GTXDRPCLK with GTP DCLK (DRP clock). Removed Conditions
entry for T_RX in Table 20. Updated V_REF column for LVDS, LVDSEXT, and LDT in Table 30. Added
T_{IDELAYPAT_JIT} to Table 36. Added Note 8 to Table 40. Replaced BUFGMUX_VIRTEX4 with BUFGCTRL in
Note 1 of Table 43. Updated description of T_FBDELAY in Table 46. In Table 70, replaced ps with ns and “All”
with XQR5VFX130.
Reduced the F_{MAX_WRITEBACK} value. Updated Notice of Disclaimer.
Updated typographical error.
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
DS692 (v1.3.1) January 16, 2015
Product Specification
www.xilinx.com
Send Feedback
41