DS692 Datasheet, PDF (30/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Clock Buffers and Networks
Table 43: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
T_{BCCCK_CE}/T_{BCCKC_CE(1)}
T_{BCCCK_S}/T_{BCCKC_S(1)}
T_{BCCKO_O}
T_{BGCKO_O}
Maximum Frequency
Description
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from I0/I1 to O
BUFG delay from I0 to O
Value
0.31/0.00
0.31/0.00
0.95
0.95
Units
ns
ns
ns
ns
F_MAX
BUFG
450
MHz
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGCTRL primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
Table 44: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
T_{BUFIOCKO_O}
Maximum Frequency
Clock to out delay from I to O
F_MAX
I/O clock tree (BUFIO)
Value
1.45
515.20
Units
ns
MHz
Table 45: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
T_{BRCKO_O}
T_{BRCKO_O_BYP}
Clock to out delay from I to O
Clock to out delay from I to O with Divide
Bypass attribute set
T_{BRDO_CLRO}
Maximum Frequency
Propagation delay from CLR to O
F_MAX
Regional clock tree (BUFR)
Value
0.75
0.26
0.92
250
Units
ns
ns
ns
MHz
DS692 (v1.3.1) January 16, 2015
Product Specification
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