DS692 Datasheet, PDF (37/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 59: Global Clock Input to Output Delay with DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, with DCM and PLL in
System-Synchronous Mode.
T_{ICKOFDCM_PLL}
Global Clock and OUTFF with DCM and PLL XQR5VFX130
4.56
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
Table 60: Global Clock Input to Output Delay with DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, with DCM and PLL in
Source-Synchronous Mode.
T_{ICKOFDCM0_PLL}
Global Clock and OUTFF with DCM and PLL XQR5VFX130
6.24
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS692 (v1.3.1) January 16, 2015
Product Specification
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