DS692 Datasheet, PDF (23/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Input/Output Delay Switching Characteristics
Table 36: Input/Output Delay Switching Characteristics
Symbol
Description
Value
T_{IDELAYPAT_JIT}
T_{IDELAYRESOLUTION}
T_{IDELAYCTRLCO_RDY}
F_{IDELAYCTRL_REF}
IDELAYCTRL_REF_PRECISION
T_{IDELAYCTRL_RPW}
T_{IODELAY_CLK_MAX}
T_{IODCCK_CE} / T_{IODCKC_CE}
T_{IODCK_INC}/ T_{IODCKC_INC}
T_{IODCK_RST}/ T_{IODCKC_RST}
Notes:
1. Average tap delay at 200 MHz = 78 ps.
Pattern dependent period jitter in delay chain for clock
pattern
Pattern dependent period jitter in delay chain for random
data pattern (PRBS 23)
IODELAY Chain Delay Resolution⁽¹⁾
Reset to Ready for IDELAYCTRL
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
0
±5
1/(64 x F_REF x 1e⁶)
3.00
200.00
±10
50.00
250
0.47/–0.06
0.27/0.07
0.37/–0.12
Units
ps
ps
ps
µs
MHz
MHz
ns
MHz
ns
ns
ns
CLB Switching Characteristics
Table 37: CLB Switching Characteristics
Symbol
Description
SET Filter⁽²⁾⁽³⁾
On
Off
Units
Combinatorial Delays
T_BYP
T_CINA
T_CINB
T_CINC
T_CIND
Sequential Delays
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
–
0.11
ns, Max
–
0.34
ns, Max
–
0.37
ns, Max
–
0.39
ns, Max
–
0.44
ns, Max
T_CKO
Clock to AQ – DQ outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
–
0.66
ns, Max
T_DICK/T_CKDI
T_RCK
T_CECK/T_CKCE
T_SRCK/T_CKSR
T_CINCK/T_CKCIN
Set/Reset
A – D input to CLK on A – D flip-flops
DX input to CLK when used as REV
CE input to CLK on A – D flip-flops
SR input to CLK on A – D flip-flops
CIN input to CLK on A – D flip-flops
2.80/0.41
2.68
3.11/–0.45
2.77/–0.03
2.47/0.35
0.70/0.41
0.58
1.01/–0.45
0.67/–0.03
0.37/0.35
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
T_SRMIN
T_RQ
T_CEO
F_TOG
SR input minimum pulse width
–
Delay from SR or REV input to AQ – DQ flip-flops
–
Delay from CE input to AQ – DQ flip-flops
–
Toggle frequency (for export control)
–
0.80
0.70
1.61
1098
ns, Min
ns, Max
ns, Max
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. For more information on SET filters, refer to DS192: Radiation-Hardened, Space-Grade Virtex-5QV Device Overview.
3. See XMP120: Quick Start Guide for Virtex-5QV FPGAs for testing limitations of redundant (fault tolerant) circuits in an XQR5VFX130 device.
Contact your local Xilinx sales representative to obtain a copy of XMP120.
DS692 (v1.3.1) January 16, 2015
Product Specification
www.xilinx.com
Send Feedback
23