DS692 Datasheet, PDF (21/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Input/Output Logic Switching Characteristics
Table 32: ILOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ICE1CK/T_ICKCE1
T_ISRCK/T_ICKSR
T_IDOCK/T_IOCKD
T_IDOCKD/T_IOCKDD
Combinatorial
T_IDI
T_IDID
Sequential Delays
T_IDLO
T_IDLOD
T_ICKQ
T_RQ
T_GSRQ
Set/Reset
T_RPW
CE1 pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY)
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using
IODELAY)
CLK to Q outputs
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Table 33: OLOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ODCK/T_OCKD
T_OOCECK/T_OCKOCE
T_OSRCK/T_OCKSR
T_OTCK/T_OCKT
T_OTCECK/T_OCKTCE
Combinatorial
T_DOQ
Sequential Delays
T_OCKQ
T_RQ
T_GSRQ
Set/Reset
T_RPW
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
D1 to OQ out or T1 to TQ out
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Value
0.66/–0.26
1.37/–0.22
0.44/–0.12
0.40/–0.08
Units
ns
ns
ns
ns
0.33
0.29
0.65
0.61
0.67
1.72
11.32
1.35
ns
ns
ns
ns
ns
ns
ns
ns, Min
Value
0.49/–0.11
0.25/–0.00
1.30/–0.13
0.46/–0.18
0.32/–0.01
0.93
0.70
2.54
11.32
1.40
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns, Min
DS692 (v1.3.1) January 16, 2015
Product Specification
www.xilinx.com
Send Feedback
21