DS692 Datasheet, PDF (28/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Configuration Switching Characteristics
Table 42: Configuration Switching Characteristics
Symbol
Description
Power-up Timing Characteristics
T_PL
Program latency
T_POR
Power-on reset (minimum/maximum)
T_ICCK
CCLK (output) delay
T_PROGRAM
Program pulse width
Master/Slave Serial Mode Programming Switching⁽¹⁾
T_DCCK/T_CCKD
T_DSCCK/T_SCCKD
T_CCO
F_MCCK
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
Maximum frequency, master mode with respect to
nominal CCLK
F_MCCKTOL
Frequency tolerance, master mode with respect to
nominal CCLK
F_MSCCK
Slave mode external CCLK
SelectMAP Mode Programming Switching⁽¹⁾
T_SMDCCK/T_SMCCKD
T_SMCSCCK/T_SMCCKCS
T_SMCCKW/T_SMWCCK
T_SMCKCSO
T_SMCO
T_SMCKBY
F_SMCCK
SelectMAP data setup/hold
CS_B setup/hold
RDWR_B setup/hold
CSO_B clock to out (330Ω pull-up resistor required)
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum frequency, master mode with respect to
nominal CCLK
F_RBCCK
Maximum Readback frequency with respect to
nominal CCLK
F_MCCKTOL
Frequency tolerance, master mode with respect to
nominal CCLK
Boundary-Scan Port Timing Specifications
T_TAPTCK
TMS and TDI setup time before TCK
T_TCKTAP
TMS and TDI hold time after TCK
T_TCKTDO
TCK falling edge to TDO output valid
F_TCK
Maximum configuration TCK clock frequency
F_TCKB
Maximum Boundary-Scan TCK clock frequency
BPI Master Flash Mode Programming Switching
T_BPICCO(4)
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
outputs valid after CCLK rising edge
T_BPIDCC/T_BPICCD
T_INITADDR
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address
cycles
SPI Master Flash Mode Programming Switching
T_SPIDCC/T_SPIDCCD
T_SPICCM
DIN setup/hold before/after the rising CCLK edge
MOSI clock to out
Value
5
10/55
300
250
4.0/0.0
4.0/0.0
7.5
100
±50
100
4.0/0.0
4.5/0.0
11.0/0.0
10
9.0
7.5
100
40
±50
1.5
3.0
6
66
66
10
3.0/0.5
3.0
4.0/0.0
10
Units
ms, Max
ms, Min/Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Max
MHz, Max
%
MHz
ns, Min
ns, Min
ns, Min
ns, Max
ns, Max
ns, Max
MHz, Max
MHz, Max
%
ns, Min
ns, Min
ns, Max
MHz, Max
MHz, Max
ns
ns
CCLK cycles
ns
ns
DS692 (v1.3.1) January 16, 2015
Product Specification
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