DS692 Datasheet, PDF (39/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 65: Global Clock Setup and Hold with PLL in Source-Synchronous Mode
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSPLL0/T_PHPLL0
No Delay Global Clock and IFF⁽²⁾ with PLL in XQR5VFX130
Source-Synchronous Mode
Value
1.51/3.01
Units
ns
Notes:
1. Setup and Hold times are measured over worst-case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 66: Global Clock Setup and Hold with DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSDCMPLL/T_PHDCMPLL
No Delay Global Clock and IFF⁽²⁾ with DCM XQR5VFX130
and PLL in System-Synchronous Mode
Value
4.01/0.67
Units
ns
Notes:
1. Setup and Hold times are measured over worst-case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0
driving PLL, PLL CLKOUT0 driving BUFG.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 67: Global Clock Setup and Hold with DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Value
Units
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,⁽¹⁾ Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics, page 14.
T_{PSDCMPLL_0}/
T_{PHDCMPLL_0}
No Delay Global Clock and IFF⁽²⁾ with DCM XQR5VFX130
and PLL in Source-Synchronous Mode
1.79/2.34
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase
adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package
skew is not included in these measurements.
2. IFF = Input Flip-Flop.
DS692 (v1.3.1) January 16, 2015
Product Specification
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