DS692 Datasheet, PDF (33/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 48: Input Clock Tolerances
Symbol
Description
Frequency Range
Value Units
Duty Cycle Input Tolerance (in %)
T_{DUTYCYCRANGE_1}
PSCLK only
T_{DUTYCYCRANGE_1_50}
T_{DUTYCYCRANGE_50_100}
T_{DUTYCYCRANGE_100_200}
PSCLK and CLKIN
T_{DUTYCYCRANGE_200_400}
T_{DUTYCYCRANGE_400}
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
T_CYCLFDLL
T_CYCLFFX
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using DFS outputs)⁽²⁾
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
T_CYCHFDLL
T_CYCHFFX
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using DFS outputs)⁽²⁾
Input Clock Period Jitter (Low Frequency Mode)
T_PERLFDLL
T_PERLFFX
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using DFS outputs)⁽²⁾
Input Clock Period Jitter (High Frequency Mode)
T_PERHFDLL
T_PERHFFX
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using DFS outputs)⁽²⁾
Feedback Clock Path Delay Variation
< 1 MHz
1 - 50 MHz
50 - 100 MHz
100 - 200 MHz
200 - 400 MHz⁽⁴⁾
> 400 MHz
25 - 75
%
25 - 75
%
30 - 70
%
40 - 60
%
45 - 55
%
45 - 55
%
345.00
ps
345.00
ps
173.00
ps
173.00
ps
1.15
ns
1.15
ns
1.15
ns
1.15
ns
T_{CLKFB_DELAY_VAR}
CLKFB off-chip feedback
1.15
ns
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. If both DLL and DFS outputs are used, follow the more restrictive specifications.
4. This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTX transceivers drive the
DCMs at 450 MHz.
DS692 (v1.3.1) January 16, 2015
Product Specification
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