DS692 Datasheet, PDF (29/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 42: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Value
T_SPICCFC
FCS_B clock to out
10
T_FSINIT/T_FSINITH
FS[2:0] to INIT_B rising edge setup and hold
2
CCLK Output (Master Modes)
T_MCCKL
T_MCCKH
CCLK Input (Slave Modes)
Master CCLK clock minimum low time
Master CCLK clock minimum high time
40/60
40/60
T_SCCKL
Slave CCLK clock minimum low time
2.0
T_SCCKH
Slave CCLK clock minimum high time
2.0
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
F_DCK
T_{DMCCK_DADDR}/T_{DMCKC_DADDR}
T_{DMCCK_DI}/T_{DMCKC_DI}
T_{DMCCK_DEN}/T_{DMCKC_DEN}
T_{DMCCK_DWE}/T_{DMCKC_DWE}
T_{DMCKO_DO}
T_{DMCKO_DRDY}/T_{DMCKCO_DRDY}
Maximum frequency for DCLK
DADDR setup/hold
DI setup/hold
DEN setup/hold time
DWE setup/hold time
CLK to out of DO⁽³⁾
CLK to out of DRDY
320
1.75/0.0
1.75/0.0
1.75/0.0
1.75/0.0
1.46
1.46
Notes:
1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
2. To support longer delays in configuration, use the design solutions described in Virtex-5 FPGA User Guide.
3. DO will hold until the next DRP operation.
4. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Units
ns
µs
%, Min/Max
%, Min/Max
ns, Min
ns, Min
MHz
ns
ns
ns
ns
ns
ns
DS692 (v1.3.1) January 16, 2015
Product Specification
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