DS692 Datasheet, PDF (34/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Output Clock Jitter
Table 49: Output Clock Jitter
Symbol
Description
Clock Synthesis Period Jitter
T_{PERJITT_0}
T_{PERJITT_90}
T_{PERJITT_180}
T_{PERJITT_270}
T_{PERJITT_2X}
T_{PERJITT_DV1}
T_{PERJITT_DV2}
T_{PERJITT_FX}
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Notes:
1. Values for this parameter are available in the Architecture Wizard.
Value
±120
±120
±120
±120
±230
±180
±350
Note ⁽¹⁾
Units
ps
ps
ps
ps
ps
ps
ps
ps
Output Clock Phase Alignment
Table 50: Output Clock Phase Alignment
Symbol
Description
Value
Units
Phase Offset Between CLKIN and CLKFB
T_{IN_FB_OFFSET}
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs⁽⁴⁾
±60
ps
T_{OUT_OFFSET_1X}
T_{OUT_OFFSET_2X}
T_{OUT_OFFSET_FX}
Duty Cycle Precision
T_{DUTY_CYC_DLL(3)}
T_{DUTY_CYC_FX}
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180, CLKDV
CLKFX, CLKFX180
DLL outputs⁽¹⁾
DFS outputs⁽²⁾
±160
ps
±200
ps
±220
ps
±180
ps
±180
ps
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.
4. All phase offsets are in respect to group CLK1X.
DS692 (v1.3.1) January 16, 2015
Product Specification
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