DS692 Datasheet, PDF (35/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 51: Miscellaneous Timing Parameters
Symbol
Description
Value
Units
Time Required to Achieve LOCK
T_{DLL_240}
T_{DLL_120_240}
T_{DLL_60_120}
T_{DLL_50_60}
T_{DLL_40_50}
T_{DLL_30_40}
T_{DLL_24_30}
T_{DLL_30}
T_{FX_MIN}
T_{FX_MAX}
T_{DLL_FINE_SHIFT}
Fine Phase Shifting
DLL output – Frequency range > 240 MHz⁽¹⁾
DLL output – Frequency range 120 - 240 MHz⁽¹⁾
DLL output – Frequency range 60 - 120 MHz⁽¹⁾
DLL output – Frequency range 50 - 60 MHz⁽¹⁾
DLL output – Frequency range 40 - 50 MHz⁽¹⁾
DLL output – Frequency range 30 - 40 MHz⁽¹⁾
DLL output – Frequency range 24 - 30 MHz⁽¹⁾
DLL output – Frequency range < 30 MHz⁽¹⁾
DFS outputs⁽²⁾
Multiplication factor for DLL lock time with Fine Shift
80.00
µs
250.00
µs
900.00
µs
1300.00
µs
2000.00
µs
3600.00
µs
5000.00
µs
5000.00
µs
10.00
ms
10.00
ms
2.00
–
T_{RANGE_MS}
Delay Lines
Absolute shifting range in maximum speed mode
7.00
ns
T_{TAP_MS_MIN}
T_{TAP_MS_MAX}
Tap delay resolution (Min) in maximum speed mode
7.00
ps
Tap delay resolution (Max) in maximum speed mode
30.00
ps
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 52: Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Min
Max
2
33
1
32
Table 53: DCM Switching Characteristics
Symbol
Description
T_{DMCCK_PSEN}/ T_{DMCKC_PSEN}
T_{DMCCK_PSINCDEC}/ T_{DMCKC_PSINCDEC}
T_{DMCKO_PSDONE}
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
Value
1.56/0.00
1.56/0.00
1.30
Units
ns
ns
ns
DS692 (v1.3.1) January 16, 2015
Product Specification
www.xilinx.com
Send Feedback
35