DS692 Datasheet, PDF (25/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 40: Block RAM and FIFO Switching Characteristics
Symbol
Description
Value
Units
Block RAM and FIFO Clock to Out Delays
T_{RCKO_DO} and T_{RCKO_DOR(1)}
Clock CLK to DOUT output (without output register)⁽²⁾⁽³⁾
Clock CLK to DOUT output (with output register)⁽⁴⁾⁽⁵⁾
Clock CLK to DOUT output with ECC (without output register)⁽²⁾⁽³⁾
Clock CLK to DOUT output with ECC (with output register)⁽⁴⁾⁽⁵⁾
Clock CLK to DOUT output with Cascade (without output register)⁽²⁾
Clock CLK to DOUT output with Cascade (with output register)⁽⁴⁾
T_{RCKO_FLAGS}
T_{RCKO_POINTERS}
Clock CLK to FIFO flags outputs⁽⁶⁾
Clock CLK to FIFO pointer outputs⁽⁷⁾
T_{RCKO_ECCR}
Clock CLK to BITERR (with output register)
T_{RCKO_ECC}
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in standard ECC mode
2.46
ns, Max
0.92
ns, Max
4.04
ns, Max
1.04
ns, Max
3.30
ns, Max
1.46
ns, Max
1.15
ns, Max
1.66
ns, Max
1.04
ns, Max
3.82
ns, Max
1.95
ns, Max
Clock CLK to ECCPARITY in ECC encode only mode
1.18
ns, Max
Setup and Hold Times Before/After Clock CLK
T_{RCCK_ADDR}/T_{RCKC_ADDR}
T_{RDCK_DI}/T_{RCKD_DI}
T_{RDCK_DI_ECC}/T_{RCKD_DI_ECC}
ADDR inputs⁽⁸⁾
DIN inputs⁽⁹⁾
DIN inputs with ECC in standard mode⁽⁹⁾
DIN inputs with ECC encode only⁽⁹⁾
0.54/0.40
0.39/0.32
0.47/0.41
0.86/0.41
ns, Min
ns, Min
ns, Min
ns, Min
T_{RCCK_EN}/T_{RCKC_EN}
T_{RCCK_REGCE}/T_{RCKC_REGCE}
T_{RCCK_SSR}/T_{RCKC_SSR}
T_{RCCK_WE}/T_{RCKC_WE}
T_{RCCK_WREN}/T_{RCKC_WREN}
Reset Delays
T_{RCO_FLAGS}
Maximum Frequency
Block RAM Enable (EN) input
CE input of output register
Synchronous Set/ Reset (SSR) input
Write Enable (WE) input
WREN/RDEN FIFO inputs⁽¹⁰⁾
Reset RST to FIFO Flags/Pointers⁽¹¹⁾
0.47/0.15
0.20/0.31
0.30/0.31
0.70/0.20
0.54/0.45
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
1.66
ns, Max
F_MAX
F_{MAX_CASCADE}
F_{MAX_FIFO}
F_{MAX_ECC}
F_{MAX_WRITEBACK}
Block RAM in all modes
Block RAM in Cascade mode
FIFO in all modes
Block RAM in ECC mode
Block RAM in ECC mode with writeback enabled
360
MHz
320
MHz
360
MHz
260
MHz
130
MHz
Notes:
1. TRACE will report all of these parameters as T_{RCKO_DO}.
2. T_{RCKO_DOR} includes T_{RCKO_DOW}, T_{RCKO_DOPR}, and T_{RCKO_DOPW} as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. T_{RCKO_DO} includes T_{RCKO_DOP} as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. T_{RCKO_FLAGS} includes these parameters: T_{RCKO_AEMPTY}, T_{RCKO_AFULL}, T_{RCKO_EMPTY}, T_{RCKO_FULL}, T_{RCKO_RDERR}, T_{RCKO_WRERR}.
7. T_{RCKO_POINTERS} includes both T_{RCKO_RDCOUNT} and T_{RCKO_WRCOUNT}.
8. The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
9. T_{RCKO_DI} includes both A and B inputs as well as the parity inputs of A and B.
10. These parameters also apply to RDEN.
11. T_{RCO_FLAGS} includes these flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
DS692 (v1.3.1) January 16, 2015
Product Specification
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