DS692 Datasheet, PDF (10/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Table 20: GTX_DUAL Tile User Clock Switching Characteristics⁽¹⁾
Symbol
Description
F_TXOUT
F_RXREC
T_RX
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
T_RX2
RXUSRCLK2 maximum frequency
T_TX
TXUSRCLK maximum frequency
T_TX2
TXUSRCLK2 maximum frequency
Conditions
Internal 20-bit datapath
Internal 16-bit datapath
1-byte interface
2-byte interface
4-byte interface
2-byte or 4-byte interface
1-byte interface
2-byte interface
4-byte interface
Value
212.5
265.625
265.625
265.625
235.625
265.625
132.813
265.625
235.625
265.625
132.813
Notes:
1. Clocking must be implemented as described in UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide.
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 21: GTX_DUAL Tile Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max Units
F_GTXTX
T_RTX
T_FTX
T_LLSKEW
V_TXOOBVDPP
T_{TXOOBTRANSITION}
T_J6.5
D_J6.5
T_J5.0
D_J5.0
T_J4.25
D_J4.25
T_J3.75
D_J3.75
T_J3.2
D_J3.2
T_J3.2L
D_J3.2L
T_J2.5
D_J2.5
T_J1.25
D_J1.25
T_J750
D_J750
T_J150
D_J150
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew⁽¹⁾
Electrical idle amplitude
Electrical idle transition time
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾⁽⁴⁾
Deterministic Jitter⁽²⁾⁽⁴⁾
Total Jitter⁽²⁾⁽⁴⁾
Deterministic Jitter⁽²⁾⁽⁴⁾
20%–80%
80%–20%
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s
3.2 Gb/s⁽³⁾
2.5 Gb/s
1.25 Gb/s
750 Mb/s
150 Mb/s
0.15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
F_GTXMAX Gb/s
120
–
ps
120
–
ps
–
350
ps
–
15
mV
–
75
ns
–
0.33
UI
–
0.17
UI
–
0.33
UI
–
0.15
UI
–
0.33
UI
–
0.14
UI
–
0.34
UI
–
0.16
UI
–
0.20
UI
–
0.10
UI
–
0.36
UI
–
0.16
UI
–
0.20
UI
–
0.08
UI
–
0.15
UI
–
0.06
UI
–
0.10
UI
–
0.03
UI
–
0.02
UI
–
0.01
UI
Notes:
1. Using the same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
3. PLL frequency at 1.6 GHz and OUTDIV = 1.
4. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
DS692 (v1.3.1) January 16, 2015
Product Specification
www.xilinx.com
Send Feedback
10