DS692 Datasheet, PDF (8/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
X-Ref Target - Figure 2
+V
0
DV_PPOUT
–V
P–N
Figure 2: Peak-to-Peak Differential Output Voltage
DS692_02_031210
Table 16 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 3 shows the single-ended input
voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
RocketIO GTX Transceiver User Guide for further details.
Table 16: GTX_DUAL Tile Clock DC Input Level Specification⁽¹⁾
Symbol
DC Parameter
V_IDIFF
V_ISE
R_IN
C_EXT
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
Notes:
1. V_MIN = 0V and V_MAX = 1200 mV.
Min
Typ
Max Units
210
800
2000 mV
105
400
1000 mV
90
105
130
Ω
–
100
–
nF
X-Ref Target - Figure 3
+V
P
N
0
X-Ref Target - Figure 4
+V
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
P–N
V_ISE
DS692_03_031510
0
V_IDIFF
–V
DS692_04_031510
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
DS692 (v1.3.1) January 16, 2015
Product Specification
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