DS692 Datasheet, PDF (24/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 38: CLB Distributed RAM Switching Characteristics
Symbol
Description
Value
Units
Sequential Delays
T_SHCKO(2)
Clock to A – B outputs
T_{SHCKO_1}
Clock to AMUX – BMUX outputs
Setup and Hold Times Before/After Clock CLK
1.99
ns, Max
2.16
ns, Max
T_DS/T_DH
T_AS/T_AH
T_WS/T_WH
T_CECK/T_CKCE
Clock CLK
A – D inputs to CLK
Address An inputs to clock
WE input to clock
CE input to CLK
1.35/0.25
0.54/0.26
0.46/–0.03
0.51/–0.07
ns, Min
ns, Min
ns, Min
ns, Min
T_MPW
T_MCP
Minimum pulse width
Minimum clock period
1.34
ns, Min
2.67
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. T_SHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 39: CLB Shift Register Switching Characteristics
Symbol
Description
Value
Units
Sequential Delays
T_REG
Clock to A – D outputs
T_{REG_MUX}
Clock to AMUX – DMUX output
T_{REG_M31}
Clock to DMUX output via M31 output
Setup and Hold Times Before/After Clock CLK
2.58
ns, Max
2.74
ns, Max
2.01
ns, Max
T_WS/T_WH
T_CECK/T_CKCE
T_DS/T_DH
Clock CLK
WE input
CE input to CLK
A – D inputs to CLK
0.29/–0.03
0.33/–0.07
0.84/0.10
ns, Min
ns, Min
ns, Min
T_MPW
Minimum pulse width
1.31
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
DS692 (v1.3.1) January 16, 2015
Product Specification
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