DS692 Datasheet, PDF (36/41 Pages) Xilinx, Inc – Radiation-Hardened

Radiation-Hardened, Space-Grade Virtex-5QV FPGA Data Sheet: DC and AC Switching Characteristics
Virtex-5QV Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 54. Values are expressed in nanoseconds unless otherwise noted.
Table 54: Global Clock Input to Output Delay without DCM or PLL
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, without DCM or PLL
T_ICKOF
Global Clock and OUTFF without DCM or PLL XQR5VFX130
9.82
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 55: Global Clock Input to Output Delay with DCM in System-Synchronous Mode
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, with DCM in System-Synchronous Mode.
T_ICKOFDCM
Global Clock and OUTFF with DCM
XQR5VFX130
4.65
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
Table 56: Global Clock Input to Output Delay with DCM in Source-Synchronous Mode
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, with DCM in Source-Synchronous Mode.
T_{ICKOFDCM_0}
Global Clock and OUTFF with DCM
XQR5VFX130
6.33
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
Table 57: Global Clock Input to Output Delay with PLL in System-Synchronous Mode
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, with PLL in System-Synchronous Mode.
T_ICKOFPLL
Global Clock and OUTFF with PLL
XQR5VFX130
4.39
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
Table 58: Global Clock Input to Output Delay with PLL in Source-Synchronous Mode
Symbol
Description
Device
Value
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, with PLL in Source-Synchronous Mode.
T_{ICKOFPLL_0}
Global Clock and OUTFF with PLL
XQR5VFX130
6.90
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
DS692 (v1.3.1) January 16, 2015
Product Specification
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