DS824 Datasheet, PDF (55/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Revision History
Date
Version
06/22/11
1.0
10/19/11
1.1
04/24/12
1.2
07/25/12
2.0
Revision
Initial Xilinx release. This document was previously released as UG783. Added additional
details in Using AXI BFM for Standalone RTL Design, page 36 and Using AXI BFM for
Embedded Designs with XPS, page 46.
Updated for Release 13.3. Added write burst address and data parameters to Table 3 and
Table 9. Added clk_delay and call_and_reset handling to Table 9. Added section on possible
scenarios in AXI BFM Example Designs, page 36.
Updated for Release 14.1. Version 2.1 of core. Core now CORE Generator compliant; added
VHDL example tests.
Updated for Vivado and Zynq features with minor document updates for v14.2
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To
the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby
DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT
LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including
your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss
of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such
damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no
obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent.
Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at
http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to
you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe
performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:
http://www.xilinx.com/warranty.htm#critapps.
DS824 July 25, 2012
www.xilinx.com
55
Product Specification