DS824 Datasheet, PDF (4/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Inferred Parameters
In addition to the parameters listed in Table 1 through Table 8, there are also parameters that are inferred for each
AXI interface in the Embedded Development Kit (EDK) tools. Through the design, these EDK-inferred parameters
control the behavior of the AXI Interconnect.
For a complete list of the interconnect settings related to the AXI interface, see DS768, LogiCORE IP AXI Interconnect
Data Sheet.
AXI3 BFMs
The AXI3 BFMs modules and files are named as follows:
• MASTER BFM
• Module Name: cdn_axi3_master_bfm
• File Name: cdn_axi3_master_bfm.v
• SLAVE BFM
• Module Name: cdn_axi3_slave_bfm
• File Name: cdn_axi3_slave_bfm.v
AXI3 Master BFM
Table 1 contains a list of parameters and configuration variables supported by the AXI3 Master BFM.
Table 1: AXI3 Master BFM Parameters
BFM Parameters
Description
NAME
String name for the master BFM. This is used in the messages coming from the
BFMs. The default for the master BFM is “MASTER_0.”
DATA_BUS_WIDTH
Read and write data buses can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
Default is 32.
ADDRESS_BUS_WIDTH
Default is 32.
ID_BUS_WIDTH
Default is 4.
MAX_OUTSTANDING_TRANSACTIONS
This defines the maximum number of outstanding transactions. Any attempt to
generate more traffic while this limit has been reached is handled by stalling until
at least one of the outstanding transactions has finished.
Default is 8.
EXCLUSIVE_ACCESS_SUPPORTED
This parameter informs the master that exclusive access is supported by the
slave. A value of 1 means it is supported so the response check expects an
EXOKAY, or else give a warning, in response to an exclusive access. A value of 0
means the slave does not support this so a response of OKAY is expected in
response to an exclusive access.
Default is 1.
WRITE_BURST_DATA_TRANSFER_GAP The configuration variable can be set dynamically during the run of a test. It
controls the gap between the write data transfers that comprise a write data burst.
This value is an integer number and is measured in clock cycles.
Default is 0.
Note: If this is set to a value greater than zero and concurrent write bursts are
called. Then write data interleaving occurs. The depth of this data interleaving
depends on the number of parallel writes being performed.
DS824 July 25, 2012
www.xilinx.com
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