DS824 Datasheet, PDF (3/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
The intended use of the AXI BFM is shown in Figure 2.
X-Ref Target - Figure 2
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Figure 2: AXI BFM Use
Figure 2 shows a single AXI BFM. However, the test bench can contain multiple instances of AXI BFMs. The DUT
and the AXI BFMs are instantiated in a test bench that also contains a clock and reset generator. Then, the test writer
instantiates the test bench into the test module and creates a test program using the BFM API layers. The test
program would call API tasks either sequentially or concurrently using fork and join. See AXI BFM Example
Designs, page 36 for practical examples of test programs and test bench setups.
Configuration Options
In most cases, the configuration options are passed to the BFM through Verilog parameters. BFM internal variables
are used for options that can be dynamically controlled by the test writer because Verilog parameters do not
support run time modifications.
To change the BFM internal variables during simulation, the correct BFM API task should be called. For example, to
change the CHANNEL_LEVEL_INFO from 0 to 1, the set_channel_level_info(1)task call should be made.
For more information on the API for changing internal variables, see Test Writing API, page 15.
DS824 July 25, 2012
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