DS824 Datasheet, PDF (38/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
AXI3 BFM Example Test Bench and Tests
The Verilog example test bench and example test for the AXI3 BFMs is shown in Figure 3.
X-Ref Target - Figure 3
CDN?AXI?EXAMPLE?TESTV
-ASTER
0ROCEDURAL"LOCK
3LAVE
0ROCEDURAL"LOCK
CDN?AXI?EXAMPLE?TBV
!8)-!34%2"&-
!8)3,!6%"&-
#ONFIGURATION
&UNCTION!0)
#HANNEL!0)
3IGNAL)NTERFACE
#ONFIGURATION
&UNCTION!0)
#HANNEL!0)
3IGNAL)NTERFACE
Figure 3: Verilog Example Test Bench and Test Case Structure
The example test bench has the master and slave BFMs connected directly to each other. This gives visibility into
both sides of the code (master code and slave code) required to hit the scenarios detailed in the example tests.
cdn_axi3_example_test.v
The example test (simulation/cdn_axi3_example_test.v) contains the master and slave test code to
simulate the following scenarios:
1. Simple sequential write and read burst transfers example
2. Looped sequential write and read transfers example
3. Parallel write and read burst transfers example
4. Narrow write and read transfers example
5. Unaligned write and read transfers example
6. Narrow and unaligned write and read transfers example
7. Out of order write and read burst example
8. Write Bursts performed in two different ways; Data before address and data with address concurrently
9. Write data interleaving example
10. Read data interleaving example
11. Outstanding transactions example
12. Slave read and write bursts error response example
13. Write and read bursts with different length gaps between data transfers example
14. Write and Read bursts with different length gaps between channel transfers example
DS824 July 25, 2012
www.xilinx.com
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Product Specification