DS824 Datasheet, PDF (42/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
cdn_axi4_lite_example_memory_mode_test.v
The example test (simulation/cdn_axi4_lite_example_memory_mode_test.v) contains the slave code to
ensure that the slave BFM is configured as a 4 KB memory model. The master code in this test writes data transfers
into the memory and reads them back. It does this with two different sets of test values.
The AXI4-Lite VHDL example test bench structure is identical to the one used for AXI3 shown in Figure 4. The
following sections provide details about the example tests available.
cdn_axi4_lite_example_test1.vhd to cdn_axi4_lite_example_test9.vhd
The example test (simulation/ cdn_axi4_lite_example_test1.vhd to
cdn_axi4_lite_example_test9.vhd) contains the master and slave test code to simulate the following
scenarios (scenario#1 is covered in Test1, scenario#2 in Test2 and so on):
1. Simple sequential write and read burst transfers example
2. Looped sequential write and read transfers example
3. Parallel write and read burst transfers example
4. Write Bursts performed in two different ways; Data before address, and data with address concurrently
5. Outstanding transactions example
6. Slave read and write bursts error response example
7. Write and Read bursts with different length gaps between channel transfers example
8. Unaligned write and read transfers example
9. Write burst that has valid data size less than the data bus width
cdn_axi4_lite_example_memory_model_test.vhd
The example test (simulation/cdn_axi4_lite_example_memory_model_test.vhd) contains the slave
code to ensure that the slave BFM is configured as a 4K memory model. The master code in this test writes data
transfers into the memory and reads them back. It does this with two different sets of test values.
AXI4-Stream BFM Example Test Bench and Tests
The AXI4-Stream Verilog example test bench structure is identical to the one used for AXI3 shown in Figure 3. The
following sections provide details about the example tests available.
cdn_axi4_streaming_example_test.v
The example test (simulation/cdn_axi4_streaming_example_test.v) contains the master and slave test
code to simulate the following scenarios:
1. Simple master to slave transfer example
2. Looped master to slave transfers example
3. Simple master to slave packet example
4. Looped master to slave packet example
5. Ragged (less data at the end of the packet than can be supported) master to slave packet example
6. Packet data interleaving example
The AXI4-Stream VHDL example test bench structure is identical to the one used for AXI3 shown in Figure 4. The
following sections provide details about the example tests available.
DS824 July 25, 2012
www.xilinx.com
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Product Specification