DS824 Datasheet, PDF (41/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
cdn_axi4_example_test1.vhd to cdn_axi4_example_test13.vhd
The example test (simulation/cdn_axi4_example_test1.vhd to cdn_axi4_example_test13.vhd)
contains the master and slave test code to simulate the following scenarios (scenario#1 is covered in Test1,
scenario#2 in Test2 and so on):
1. Simple sequential write and read burst transfers example
2. Looped sequential write and read transfers example
3. Parallel write and read burst transfers example
4. Narrow write and read transfers example
5. Unaligned write and read transfers example
6. Narrow and unaligned write and read transfers example
7. Write Bursts performed with address and data channel transfers concurrently
8. Outstanding transactions example
9. Slave read and write bursts error response example
10. Write and read bursts with different length gaps between data transfers example
11. Write and Read bursts with different length gaps between channel transfers example
12. Write burst that is longer than the data it is sending example
13. Read data interleaving example
cdn_axi4_example_memory_model_test.vhd
The example test (simulation/cdn_axi4_example_memory_model_test.vhd) contains the slave code to
ensure that the slave BFM is configured as a 4K memory model. The master code in this test writes maximum length
bursts into the memory and reads them back. It does this with two different sets of test values.
AXI4-Lite BFM Example Test Bench and Tests
The AXI4-Lite Verilog example test bench structure is identical to the one used for AXI3 shown in Figure 3. The
following sections provide details about the example tests available.
cdn_axi4_lite_example_test.v
The example test (simulation/cdn_axi4_lite_example_test.v) contains the master and slave test code to
simulate the following scenarios:
1. Simple sequential write and read burst transfers example
2. Looped sequential write and read transfers example
3. Parallel write and read burst transfers example
4. Write Bursts performed in two different ways; Data before address, and data with address concurrently
5. Outstanding transactions example
6. Slave read and write bursts error response example
7. Write and Read bursts with different length gaps between channel transfers example
8. Unaligned write and read transfers example
9. Write burst that has valid data size less than the data bus width
DS824 July 25, 2012
www.xilinx.com
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Product Specification