DS824 Datasheet, PDF(2/55 Page) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

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DS824 Datasheet, PDF (2/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

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LogiCORE IP AXI Bus Functional Models (v3.00.a)

Overview

The general AXI BFM architecture is shown in Figure 1.

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Figure 1: AXI BFM Architecture

All of the AXI BFMs consist of three main layers:

â¢ Signal interface

â¢ Channel API

â¢ Function API

The signal interface includes the typical Verilog input/output ports and associated signals. The channel API is a set

of defined Verilog tasks (see Test Writing API, page 15) that operate at the basic transaction level inherent in the AXI

protocol, including:

â¢ Read Address Channel

â¢ Write Address Channel

â¢ Read Data Channel

â¢ Write Data Channel

â¢ Write Response Channel

This split enables the tasks associated with each channel to be executed concurrently or sequentially. This allows the

test writer to control and implement out of order transfers, interleaved data transfers, and other features.

The next level up in the API hierarchy is the function level API (see Test Writing API, page 15). This level has

complete transaction level control. For example, a complete AXI read burst process is encapsulated in a single

Verilog task.

One final but important piece of the AXI BFM architecture is the configuration mechanism. This is implemented

using Verilog parameters and/or BFM internal variables and is used to set the address bus width, data bus width,

and other parameters. The reason Verilog parameters are used instead of defines is so that each BFM can be

configured separately within a single test bench. For example, it is reasonable to have an AXI master that has a

different data bus width than one of the slaves it is attached to (in this case the interconnect needs to handle this).

BFM internal variables are used for configuration variables that maybe changed during simulation. For a complete

list of configuration options, see Configuration Options, page 3.

DS824 July 25, 2012

www.xilinx.com

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