DS824 Datasheet, PDF (32/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Table 19: Function Level API for AXI4-Lite Master BFM (Cont’d)
API Task Name and Description
Inputs
Outputs
WRITE_BURST_CONCURRENT
This task does the same function as the
WRITE_BURST task; however, it performs the
write address and data phases concurrently.
ADDR: Write Address
PROT: Protection Type
DATA: Data to send
DATASIZE: The size in bytes of the
valid data contained in the input data
vector
RESPONSE: The slave write response
from the following: [OKAY, SLVERR,
DECERR]
WRITE_BURST_DATA_FIRST
This task does the same function as the
WRITE_BURST task; however, it sends the
write data burst before sending the associated
write address transfer on the write address
channel.
ADDR: Write Address
PROT: Protection Type
DATA: Data to send
DATASIZE: The size in bytes of the
valid data contained in the input data
vector
RESPONSE: The slave write response
from the following: [OKAY, SLVERR,
DECERR]
AXI4-Lite Slave BFM Test Writing API
The channel level API for the AXI4-Lite Slave BFM is detailed in Table 20.
Table 20: Channel Level API for AXI4-Lite Slave BFM
API Task Name and Description
Inputs
Outputs
SEND_WRITE_RESPONSE
Creates a write response channel transaction.
This task returns after it has been acknowledged
by the master.
This task emits a
“write_response_transfer_complete” event upon
completion.
RESPONSE: The chosen write
response from the following [OKAY,
SLVERR, DECERR]
None
SEND_READ_DATA
Creates a read channel transaction. This task
returns after it has been acknowledged by the
master.
This task emits a “read_data_transfer_complete”
event upon completion.
DATA: Data to send to the master
RESPONSE: The read response to
send to the master from the following:
[OKAY, SLVERR, DECERR]
None
RECEIVE_WRITE_ADDRESS
This task drives the AWREADY signal and
monitors the write address bus for write address
transfers coming from the master. It returns the
data associated with the write address
transaction.
This task uses the SLAVE_ADDRESS and
SLAVE_MEM_SIZE parameters to determine if
the address is valid.
This task emits a
“write_address_transfer_complete” event upon
completion.
ADDR: Write Address
ADDRValid: Bit to indicate if the
address input parameter is to be
used. When set to 1 the ADDR is
valid and used, when set to 0 it is
ignored.
PROT: Protection Type
SADDR: Sampled Write Address
DS824 July 25, 2012
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