DS824 Datasheet, PDF (35/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
AXI4-Stream Slave BFM Test Writing API
The channel level API for the AXI4-Stream Slave BFM is detailed in Table 23.
Table 23: Channel Level API for AXI4-Stream Slave BFM
API Task Name and Description
Inputs
Outputs
RECEIVE_TRANSFER
Receives a single AXI4-Stream transfer.
This task emits a “transfer_complete” event
upon completion.
None
ID: Transfer ID Tag
DEST: Transfer Destination
DATA: Transfer Data
STRB: Transfer Strobe Signals
KEEP: Transfer Keep Signals
LAST: Transfer Last Signal
USER: Transfer User Signals
RECEIVE_PACKET
This task receives and processes a packet
from the transfer channel. It returns when
the complete packet has been sampled, and
emits a “packet_complete” event upon
completion.
This task uses the RECEIVE_TRANSFER
task from the channel level API.
If the IDValid or DESTValid bits are 0, the
input ID tag and the DEST values are not
used. In this case, the next values from the
first valid transfer are sampled and used for
the full packet irrespective of the ID tag or
DEST input values.
ID: Packet ID Tag
IDValid: Bit to indicate if the ID input
parameter is to be used. When set to 1,
the ID is valid and used; when set to 0,
it is ignored
DEST: Packet Destination
DESTValid: Bit to indicate if the DEST
input parameter is to be used
PID: Packet ID Tag
PDEST: Packet Destination
DATA: Packet data vector
DATASIZE: The size in bytes of the valid
data contained in the output packet data
vector
USER: This is a vector that is created by
concatenating all master user signal
data together
Protocol Checking
The purpose of the AXI BFMs is to verify connectivity and basic functionality of AXI masters and AXI slaves. A
basic level of protocol checking is included with the AXI BFMs. For comprehensive protocol checking, the Cadence
AXI UVC should be deployed [Ref 4].
The following aspects of the AXI3 and AXI4 protocol are checked by the AXI BFMs:
• Reset conditions are checked:
• Reset values of signals
• Synchronous release of reset
• Inputs into the test writing API are checked to ensure they are valid to prevent protocol violations.
• Signal inputs into master and slave BFMs, respectively, are checked to ensure they are valid to prevent protocol
violations.
• Address ranges are checked in the Slave BFMs.
This section describes the checkers that are implemented as Verilog tasks.
BFM Specific Checkers
Table 24 details the Verilog checking tasks added to each BFM for a specific check. These checkers are only required
for the BFM that they are located in; so, they are not included in a common file.
DS824 July 25, 2012
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Product Specification