DS824 Datasheet, PDF (44/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
cycles through burst lengths of 1 to 16. For exhaustive WRAP tests, another for loop declaration is widely used to
drive legal stimulus:
for (i=2; i <= 16; i=i*2) begin
thus giving a burst length of 2, 4, 8 and 16 transfers.
DUT Modeling Using the AXI BFMs – Memory Model Example
In most cases, the behavior of a master or slave is more complicated than simple transfer generation. For this reason,
the AXI BFM API enables the end user to model higher level DUT functionality. A simple example is a slave
memory model. Such a memory model is available as a configuration option in most of the AXI slave BFMs. This
example shows the code used for the AXI3 Slave BFM memory model mode, starting with the write datapath.
//------------------------------------------------------------------// Write Path
//------------------------------------------------------------------
always @(posedge ACLK) begin : WRITE_PATH
//----------------------------------------------------------------
//- Local Variables
//----------------------------------------------------------------
reg [ID_BUS_WIDTH-1:0] id;
reg [ADDRESS_BUS_WIDTH-1:0] address;
reg [`LENGTH_BUS_WIDTH-1:0] length;
reg [`SIZE_BUS_WIDTH-1:0] size;
reg [`BURST_BUS_WIDTH-1:0] burst_type;
reg [`LOCK_BUS_WIDTH-1:0] lock_type;
reg [`CACHE_BUS_WIDTH-1:0] cache_type;
reg [`PROT_BUS_WIDTH-1:0] protection_type;
reg [ID_BUS_WIDTH-1:0] idtag;
reg [(DATA_BUS_WIDTH*(`MAX_BURST_LENGTH+1))-1:0] data;
reg [ADDRESS_BUS_WIDTH-1:0] internal_address;
reg [`RESP_BUS_WIDTH-1:0] response;
integer i;
integer datasize;
//----------------------------------------------------------------
// Implementation Code
//----------------------------------------------------------------
if (MEMORY_MODEL_MODE == 1) begin
// Receive the next available write address
RECEIVE_WRITE_ADDRESS(id,`IDVALID_FALSE,address,length,size,
burst_type,lock_type,cache_type,protection_type,idtag);
// Get the data to send to the memory.
RECEIVE_WRITE_BURST(idtag,`IDVALID_TRUE,address,length,size,
burst_type,data,datasize,idtag);
// Put the data into the memory array
internal_address = address - SLAVE_ADDRESS;
for (i=0; i < datasize; i=i+1) begin
memory_array[internal_address+i] = data[i*8 +: 8];
end
// End the complete write burst/transfer with a write response
// Work out which response type to send based on the lock type.
response = calculate_response(lock_type);
repeat(WRITE_RESPONSE_GAP) @(posedge ACLK);
SEND_WRITE_RESPONSE(idtag,response);
end
end
As shown in the code above, it is possible to create the write datapath for a simple memory model using three of the
tasks from the slave channel level API. This is achieved in the following four steps:
DS824 July 25, 2012
www.xilinx.com
44
Product Specification