DS824 Datasheet, PDF (36/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Table 24: BFM Specific Checker Tasks
Checker Task Name
Inputs
check_address_range ADDRESS
BURST_TYPE
LENGTH
check_strobe
STROBE
TRANSFER_NUMBER
ADDRESS
LENGTH
SIZE
BURST_TYPE
Checker
Location/s
SLAVE BFM
SLAVE BFM
Description
Checks to see if address is valid with respect to the SLAVE
configuration, the burst_type and length.
Checks to see if the input strobe is correct. This check
handles normal, narrow and unaligned transfers.
Using AXI BFM for Standalone RTL Design
The AXI BFM can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the
custom RTL design flow. The AXI BFM provides example test benches and tests that demonstrate the abilities of
AXI3, AXI4, AXI4-Lite and AXI4-Stream Master/Slave BFM pair. These examples can be used as a starting point to
create tests for custom RTL design with AXI3, AXI4, AXI4-Lite and AXI4-Stream interface.
Generating AXI BFM Examples and Test Benches from CORE Generator
The AXI BFM is delivered with ISE Design Suite installation at:
• <ISE_Version_Number>/ise_ds/ise/secureip/mti/axi_bfm_mti
• <ISE_Version_Number>/ise_ds/ise/secureip/ncsim/axi_bfm_ncsim
• <ISE_Version_Number>/ise_ds/ise/secureip/vcs/axi_bfm_vcs
• <ISE_Version_Number>/ise_ds/ise/secureip/aldec/axi_bfm_aldec
The examples and test benches can be obtained by generating the AXI BFM IP available in the “AXI Infrastructure”
or “Debug & Verification” folder of the CORE Generator™ IP catalog. When generated, the AXI BFM IP delivers the
user-specified <component_name> directory.
The <component_name>/simulation/functional directory contains the shell scripts for different simulators.
Shell Script
Simulator
simulate_isim.sh ISim
simulate_mti.sh Mentor Graphics ModelSim
simulate_ncsim.sh Cadence IES
simulate_vcs.sh Synopsys VCS
simulate_aldec.sh Aldec Riviera-PRO
AXI BFM Example Designs
This section describes the example test benches and example tests used to demonstrate the abilities of each AXI
BFM pair. Example tests are delivered either in VHDL or Verilog based on the design entry while generating the
core. These example designs are available in the AXI_BFM installation area. Each AXI master is connected to a
single AXI slave, and then direct tests are used to transfer data from the master to the slave and from the slave to the
master.
DS824 July 25, 2012
www.xilinx.com
36
Product Specification