DS824 Datasheet, PDF (54/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

X-Ref Target - Figure 16
LogiCORE IP AXI Bus Functional Models (v3.00.a)
Figure 16: BFM_Lite_Processor Read Waveform
In Figure 16, BFM_Lite_Processor issues a single Read command to my_axi_ip, and my_axi_ip responds with
read data.
As a result of these transactions, the ModelSim console outputs:
# ----------------------------------------------------
# Full Registers write followed by a full Registers read
# ----------------------------------------------------
# Writing to Slave Register addr=0x30000000 data=0x03020100
# Reading from Slave Register addr=0x30000000 data=0x03020100
References
These documents provide supplemental material useful with this product guide:
1. DS768, LogiCORE IP AXI Interconnect Data Sheet
2. UG814, Vivado Design Suite Getting Started Guide
3. ARM® AMBA® AXI Protocol v2.0 Specification (ARM IHI 0022C)
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022c/index.html
4. Cadence AXI UVC User Guide (VIPP 9.2/VIPP 10.2 releases)
Technical Support
Xilinx provides technical support at www.xilinx.com/support for this LogiCORE IP product when used as
described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of product if
implemented in devices that are not defined in the documentation, if customized beyond that allowed in the
product documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
See the IDS Embedded Edition Derivative Device Support web page
(www.xilinx.com/ise/embedded/ddsupport.htm) for a complete list of supported derivative devices for
this core.
Licensing Ordering Information
This Xilinx LogiCORE IP module is provided under the terms of the Xilinx Core License Agreement. The module is
shipped as part of the Vivado Design Suite and ISE Design Suite. For full access to all core functionalities in
simulation, you must purchase a license for the core. Contact your local Xilinx sales representative for information
on pricing and availability.
For more information, visit the AXI Bus Functional Model web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For
information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx
sales representative.
DS824 July 25, 2012
www.xilinx.com
54
Product Specification