DS824 Datasheet, PDF (37/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
It is worth remembering that the BFMs are not fully autonomous. For example, the AXI Master BFM is only a
user-driven verification component that enables the user to generate valid AXI protocol scenarios. Furthermore, if
tests are written using the channel level API it is possible that the AXI protocol can be accidentally violated. For this
reason, Xilinx recommends using the function level API for each BFM. The AMBA AXI protocol specification
[Ref 3], Section 3.3, Dependencies between Channel Handshake Signals, states that:
• Slave can wait for AWVALID or WVALID, or both, before asserting AWREADY
• Slave can wait for AWVALID or WVALID, or both, before asserting WREADY
This implies that the slave does not need to support all three possible scenarios. However, if the AXI Master BFM
operates in such a way that is not supported by the slave, then the simulation stalls. Each scenario is handled by the
function level API:
Scenario 1
Before the slave asserts AWREADY and/or WREADY, the slave can wait for AWVALID. This is modeled using the
function level API, WRITE_BURST.
Scenario 2
Before the slave asserts AWREADY and/or WREADY, the slave can wait for WVALID. This is modeled using the
function level API, WRITE_BURST_DATA_FIRST.
Scenario 3
Before the slave asserts AWREADY and/or WREADY, the slave can wait for both AWVALID and WVALID. This is
modeled using the function level API, WRITE_BURST_CONCURRENT.
DS824 July 25, 2012
www.xilinx.com
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Product Specification