DS824 Datasheet, PDF (24/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Table 14: Channel Level API for AXI4 Master BFM (Cont’d)
API Task Name
Inputs
SEND_READ_ADDRESS
Creates a read address channel transaction. This task returns
after the read address has been acknowledged by the slave.
This task emits a “read_address_transfer_complete” event
upon completion.
ID: Read Address ID tag
ADDR: Read Address
LEN: Burst Length
SIZE: Burst Size
BURST: Burst Type
LOCK: Lock Type
CACHE: Cache Type
PROT: Protection Type
REGION: Region Identifier
QOS: Quality of Service Signals
ARUSER: Address Read User
Defined Signals
RECEIVE_READ_DATA
This task drives the RREADY signal and monitors the read
data bus for read transfers coming from the slave that have the
specified ID tag. It then returns the data associated with the
transaction and the status of the last flag. The data output here
is raw bus data; that is, no realignment for narrow or unaligned
data.
This task emits a “read_data_transfer_complete” event upon
completion.
Note: This would need to be called multiple times for a burst
> 1.
ID: Read ID tag
Also, the user must call the "remove_pending_transaction"
task when all data is received to ensure that the pending
transaction counter is decremented. This is done
automatically by the RECEIVE_READ_BURST and
RECEIVE_WRITE_RESPONSE channel level API tasks.
RECEIVE_WRITE_RESPONSE
This task drives the BREADY signal and monitors the write
response bus for write responses coming from the slave that
have the specified ID tag. It then returns the response
associated with the transaction.
This task emits a “write_response_transfer_complete” event
upon completion.
ID: Write ID tag
Outputs
None
DATA: Data transferred by
the slave
RESPONSE: The slave
read response from the
following: [OKAY, EXOKAY,
SLVERR, DECERR]
LAST: Last transfer flag
RUSER: Read User
Defined Signals
RESPONSE: The slave
write response from the
following: [OKAY, EXOKAY,
SLVERR, DECERR]
BUSER: Write Response
User Defined Signals
DS824 July 25, 2012
www.xilinx.com
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