DS824 Datasheet, PDF (45/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
1. The first step is to wait for any write address request on the write address bus. This is done by calling
RECEIVE_WRITE_ADDRESS with “IDVALID_FALSE.” This ensures that the first detected and valid write
address handshake is recorded and the details passed back. This task is blocking; so the WRITE_PATH process
does not proceed until it has found a write address channel transfer.
2. The second step is to get the write data burst that corresponds to the write address request in the previous step.
This is done by calling RECEIVE_WRITE_BURST with the ID tag output from the
RECEIVE_WRITE_ADDRESS call and with IDVALID_TRUE. This ensures that the entire write data burst that
has the specified id tag is captured before execution returns to the WRITE_PATH process.
3. The third step is to take the data from the write data burst and put it into a memory array. In this case, the
memory array is an array of bytes.
4. The last step to complete the AXI3 protocol is to send a response. The internal function “calculate_reponse” is
used to work out if the transfer was exclusive or not and to deliver an EXOKAY or OK response (more code
could be added here to support DECERR or SLVERR response types). When the response has been calculated,
the WRITE_PATH process waits for the defined internal control variable WRITE_RESPONSE_GAP in clock
cycles before sending the response back to the slave with the same ID tag as the write data transfer.
The following code illustrates the steps required to make the read datapath for a simple slave memory model:
//-----------------------------------------------------------------
// Read Path
//-----------------------------------------------------------------always @(posedge ACLK)
begin : READ_PATH
//---------------------------------------------------------------
// Local Variables
//---------------------------------------------------------------
reg [ID_BUS_WIDTH-1:0] id;
reg [ADDRESS_BUS_WIDTH-1:0] address;
reg [`LENGTH_BUS_WIDTH-1:0] length;
reg [`SIZE_BUS_WIDTH-1:0] size;
reg [`BURST_BUS_WIDTH-1:0] burst_type;
reg [`LOCK_BUS_WIDTH-1:0] lock_type;
reg [`CACHE_BUS_WIDTH-1:0] cache_type;
reg [`PROT_BUS_WIDTH-1:0] protection_type;
reg [ID_BUS_WIDTH-1:0] idtag;
reg [(DATA_BUS_WIDTH*(`MAX_BURST_LENGTH+1))-1:0] data;
reg [ADDRESS_BUS_WIDTH-1:0] internal_address;
integer i;
integer number_of_valid_bytes;
//---------------------------------------------------------------
// Implementation Code
//---------------------------------------------------------------
if (MEMORY_MODEL_MODE == 1) begin
// Receive a read address transfer
RECEIVE_READ_ADDRESS(id,`IDVALID_FALSE,address,length,size,
burst_type,lock_type,cache_type,protection_type,idtag);
// Get the data to send from the memory.
internal_address = address - SLAVE_ADDRESS;
data = 0;
number_of_valid_bytes =
(decode_burst_length(length)*transfer_size_in_bytes(size))-(address % (DATA_BUS_WIDTH/8));
for (i=0; i < number_of_valid_bytes; i=i+1) begin
data[i*8 +: 8] = memory_array[internal_address+i];
end
// Send the read data
repeat(READ_RESPONSE_GAP) @(posedge ACLK);
SEND_READ_BURST(idtag,address,length,size,burst_type,
DS824 July 25, 2012
www.xilinx.com
45
Product Specification