DS824 Datasheet, PDF (34/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Table 21: Function Level API for AXI4-Lite Slave BFM (Cont’d)
API Task Name and Description
Inputs
Outputs
READ_BURST_RESP_CTRL
This task is the same as
READ_BURST_RESPOND except that the
response sent to the master can be specified.
ADDR: Read Address
ADDRValid: Bit to indicate if the
address input parameter is to be used.
When set to 1 the ADDR is valid and
used, when set to 0 it is ignored.
DATA: Data to send in response to the
master read
RESPONSE: The chosen write
response from the following [OKAY,
SLVERR, DECERR]
None
WRITE_BURST_RESP_CTRL
This task is the same as
WRITE_BURST_RESPOND except that the
response sent to the master can be specified.
ADDR: Write Address
ADDRValid: Bit to indicate if the
address input parameter is to be used.
When set to 1 the ADDR is valid and
used, when set to 0 it is ignored.
RESPONSE: The chosen write
response from the following [OKAY,
SLVERR, DECERR]
DATA: Data received by slave
DATASIZE: The size in bytes of
the valid data contained in the
output data vector
AXI4-Stream Master BFM Test Writing API
The channel level API for the AXI4-Stream Master BFM is detailed in Table 22.
Table 22: Channel Level API for AXI4-Stream Master BFM
API Task Name and Description
Inputs
SEND_TRANSFER
Creates a single AXI4-Stream transfer.
This task emits a “transfer_complete” event upon
completion.
ID: Transfer ID Tag
DEST: Transfer Destination
DATA: Transfer Data
STRB: Transfer Strobe Signals
KEEP: Transfer Keep Signals
LAST: Transfer Last Signal
USER: Transfer User Signals
None
SEND_PACKET
This task sends a complete packet over the
streaming interface. It uses the SEND_TRANSFER
task from the channel level API.
This task returns when the whole packet has been
sent, and emits a “packet_complete” event upon
completion.
ID: Transfer ID Tag
DEST: Transfer Destination
DATA: Vector of Transfer data to send
DATASIZE: The size in bytes of the valid
data contained in the input data vector
(This must be aligned to the multiples of
the data bus width)
USER: This is a vector that is created
by concatenating all transfer user signal
data together
None
Outputs
DS824 July 25, 2012
www.xilinx.com
34
Product Specification