DS824 Datasheet, PDF (33/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
Table 20: Channel Level API for AXI4-Lite Slave BFM (Cont’d)
API Task Name and Description
Inputs
RECEIVE_READ_ADDRESS
This task drives the ARREADY signal and
monitors the read address bus for read address
transfers coming from the master. It returns the
data associated with the read address
transaction.
This task uses the SLAVE_ADDRESS and
SLAVE_MEM_SIZE parameters to determine if
the address is valid.
This task emits a
“read_address_transfer_complete” event upon
completion.
ADDR: Read Address
ADDRValid: Bit to indicate if the
address input parameter is to be
used. When set to 1 the ADDR is
valid and used, when set to 0 it is
ignored.
RECEIVE_WRITE_DATA
This task drives the WREADY signal and
monitors the write data bus for write transfers
coming from the master. It returns the data
associated with the transaction.
This task emits a
“write_data_transfer_complete” event upon
completion.
None
Outputs
PROT: Protection Type
SADDR: Sampled Read Address
DATA: Data transferred from the
master
STRB: Strobe signals used to
validate the data
The function level API for the AXI4-Lite Slave BFM is detailed in Table 21.
Table 21: Function Level API for AXI4-Lite Slave BFM
API Task Name and Description
Inputs
Outputs
READ_BURST_RESPOND
Creates a semi-automatic response to a read
request from the master. It is composed of the tasks
RECEIVE_READ_ADDRESS and
SEND_READ_DATA from the channel level API.
This task returns when the complete write
transaction is complete.
If ADDRVALID = 0 the input ADDR is ignored and
the first read request is used and responded to.
If the ADDRVALID = 1 then the ADDR input is used
and the DATA input is used to respond to the read
burst with the specified address.
ADDR: Read Address
ADDRValid: Bit to indicate if the
address input parameter is to be used.
When set to 1 the ADDR is valid and
used, when set to 0 it is ignored.
DATA: Data to send in response to the
master read
None
WRITE_BURST_RESPOND
This is a semi-automatic task which waits for a write
burst from the master and responds appropriately.
The data received in the write burst is delivered as
an output data vector.
This task is composed of the tasks
RECEIVE_WRITE_ADDRESS,
RECEIVE_WRITE_DATA and
SEND_WRITE_RESPONSE from the channel level
API.
This task returns when the complete write
transaction is complete.
If ADDRVALID = 0 the input ADDR is ignored and
the first write request is used for the DATA output.
If the ADDRVALID = 1 then the ADDR input is used
and the DATA associated with that transfer is output
using the DATA output.
ADDR: Write Address
ADDRValid: Bit to indicate if the
address input parameter is to be used.
When set to 1 the ADDR is valid and
used, when set to 0 it is ignored.
DATA: Data received by slave
DATASIZE: The size in bytes of
the valid data contained in the
output data vector
DS824 July 25, 2012
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