DS824 Datasheet, PDF (27/55 Pages) Xilinx, Inc – LogiCORE IP AXI Bus Functional Models (v3.00.a)

LogiCORE IP AXI Bus Functional Models (v3.00.a)
AXI4 Slave BFM Test Writing API
The channel level API for the AXI4 Slave BFM is detailed in Table 16.
Table 16: Channel Level API for AXI4 Slave BFM
API Task Name
Inputs
Outputs
SEND_WRITE_RESPONSE
Creates a write response channel transaction. The ID tag
must match the associated write transaction. This task
returns after it has been acknowledged by the master.
This task emits a “write_response_transfer_complete”
event upon completion.
ID: Write ID tag
RESPONSE: The chosen write
response from the following
[OKAY, EXOKAY, SLVERR,
DECERR]
BUSER: Write Response User
Defined Signals
None
SEND_READ_DATA
Creates a read channel transaction. The ID tag must
match the associated read transaction. This task returns
after it has been acknowledged by the master.
This task emits a “read_data_transfer_complete” event
upon completion.
Note: This would need to be called multiple times for a
burst > 1.
ID: Read ID tag
DATA: Data to send to the master
RESPONSE: The read response
to send to the master from the
following: [OKAY, EXOKAY,
SLVERR, DECERR]
LAST: Last transfer flag
RUSER: Read User Defined
Signals
None
RECEIVE_WRITE_ADDRESS
This task drives the AWREADY signal and monitors the
write address bus for write address transfers coming from
the master that have the specified ID tag (unless the
IDValid bit = 0). It then returns the data associated with the
write address transaction.
If the IDValid bit is 0 then the input ID tag is not used and
the next available write address transfer is sampled.
This task uses the SLAVE_ADDRESS and
SLAVE_MEM_SIZE parameters to determine if the
address is valid.
This task emits a “write_address_transfer_complete”
event upon completion.
ID: Write Address ID tag
IDValid: Bit to indicate if the ID
input parameter is to be used.
When set to 1 the ID is valid and
used, when set to 0 it is ignored.
ADDR: Write Address
LEN: Burst Length
SIZE: Burst Size
BURST: Burst Type
LOCK: Lock Type
CACHE: Cache Type
PROT: Protection Type
REGION: Region Identifier
QOS: Quality of Service
Signals
AWUSER: Address Write User
Defined Signals
IDTAG: Sampled ID tag
RECEIVE_READ_ADDRESS
This task drives the ARREADY signal and monitors the
read address bus for read address transfers coming from
the master that have the specified ID tag (unless the
IDValid bit = 0). It then returns the data associated with the
read address transaction.
If the IDValid bit is 0 then the input ID tag is not used and
the next available read address transfer is sampled.
This task uses the SLAVE_ADDRESS and
SLAVE_MEM_SIZE parameters to determine if the
address is valid.
This task emits a “read_address_transfer_complete”
event upon completion.
ID: Read Address ID tag
IDValid: Bit to indicate if the ID
input parameter is to be used.
When set to 1 the ID is valid and
used, when set to 0 it is ignored.
ADDR: Read Address
LEN: Burst Length
SIZE: Burst Size
BURST: Burst Type
LOCK: Lock Type
CACHE: Cache Type
PROT: Protection Type
REGION: Region Identifier
QOS: Quality of Service
Signals
ARUSER: Address Read User
Defined Signals
IDTAG: Sampled ID tag
DS824 July 25, 2012
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Product Specification