LM3S1G21 Datasheet, PDF (905/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
21.13
External Peripheral Interface (EPI)
When the EPI module is in SDRAM mode, the drive strength must be configured to 8 mA. Table
21-21 on page 905 shows the rise and fall times in SDRAM mode with 16 pF load conditions. When
the EPI module is in Host-Bus or General-Purpose mode, the values in “Input/Output
Characteristics” on page 904 should be used.
Table 21-21. EPI SDRAM Characteristics
Parameter Parameter Name
Condition
Min
T_SDRAMR EPI Rise Time (from 20% to 80% of 8-mA drive, C_L = 16 pF
-
V_DD)
T_SDRAMF
EPI Fall Time (from 80% to 20% of 8-mA drive, C_L = 16 pF
-
V_DD)
Nom
2
2
Max
3
3
Table 21-22. EPI SDRAM Interface Characteristics^a
Parameter No Parameter
Parameter Name
E1
T_CK
SDRAM Clock period
E2
T_CH
SDRAM Clock high time
E3
T_CL
SDRAM Clock low time
E4
T_COV
CLK to output valid
E5
T_COI
CLK to output invalid
E6
T_COT
CLK to output tristate
E7
T_S
Input set up to CLK
E8
T_H
CLK to input hold
E9
T_PU
Power-up time
E10
T_RP
Precharge all banks
E11
T_RFC
Auto refresh
E12
T_MRD
Program mode register
a. The EPI SDRAM interface must use 8-mA drive.
Min
Nom Max
20
-
-
10
-
-
10
-
-
-5
-
5
-5
-
5
-5
-
5
10
-
-
0
-
-
100
-
-
20
-
-
66
-
-
40
-
-
Unit
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Figure 21-13. SDRAM Initialization and Load Mode Register Timing
CLK
(EPI0S31)
E1
CKE
(EPI0S30)
Command
(EPI0S[29:28,19:18])
NOP
PRE
DQMH, DQML
(EPI0S[17:16])
AD11, AD[9:0]
(EPI0S[11,9:0]
AD10
(EPI0S[10])
BAD[1:0]
(EPI0S[14:13])
All Banks
Single Bank
AD [15,12]
(EPI0S [15,12])
E9
E10
NOP
E11
E2
AREF
E3
NOP
PRE
E12
Notes:
1. If CS is high at clock high time, all applied commands are NOP.
2. The Mode register may be loaded prior to the auto refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
NOP
AREF
NOP
LOAD
Code
Code
NOP
AREF
NOP
Active
Row
Row
Bank
January 22, 2012
905
Texas Instruments-Production Data