LM3S1G21 Datasheet, PDF (12/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Table of Contents
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 751
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 752
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 753
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 753
Figure 16-1. I²C Block Diagram ............................................................................................. 785
Figure 16-2. I²C Bus Configuration ........................................................................................ 786
Figure 16-3. START and STOP Conditions ............................................................................. 787
Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 787
Figure 16-5. R/S Bit in First Byte ............................................................................................ 788
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 788
Figure 16-7. Master Single TRANSMIT .................................................................................. 792
Figure 16-8. Master Single RECEIVE ..................................................................................... 793
Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 794
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 795
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 796
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 797
Figure 16-13. Slave Command Sequence ................................................................................ 798
Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 822
Figure 17-2. Structure of Comparator Unit .............................................................................. 824
Figure 17-3. Comparator Internal Reference Structure ............................................................ 825
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 835
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 836
Figure 21-1. Load Conditions ................................................................................................ 895
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 896
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 896
Figure 21-4. Power-On Reset Timing ..................................................................................... 897
Figure 21-5. Brown-Out Reset Timing .................................................................................... 897
Figure 21-6. Power-On Reset and Voltage Parameters ........................................................... 898
Figure 21-7. External Reset Timing (RST) .............................................................................. 898
Figure 21-8. Software Reset Timing ....................................................................................... 898
Figure 21-9. Watchdog Reset Timing ..................................................................................... 899
Figure 21-10. MOSC Failure Reset Timing ............................................................................... 899
Figure 21-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 903
Figure 21-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 904
Figure 21-13. SDRAM Initialization and Load Mode Register Timing .......................................... 905
Figure 21-14. SDRAM Read Timing ......................................................................................... 906
Figure 21-15. SDRAM Write Timing ......................................................................................... 906
Figure 21-16. Host-Bus 8/16 Mode Read Timing ...................................................................... 907
Figure 21-17. Host-Bus 8/16 Mode Write Timing ....................................................................... 907
Figure 21-18. Host-Bus 8/16 Mode Muxed Read Timing ............................................................ 908
Figure 21-19. Host-Bus 8/16 Mode Muxed Write Timing ............................................................ 908
Figure 21-20. General-Purpose Mode Read and Write Timing ................................................... 909
Figure 21-21. General-Purpose Mode iRDY Timing .................................................................. 909
Figure 21-22. ADC Input Equivalency Diagram ......................................................................... 911
Figure 21-23. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 912
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January 22, 2012
Texas Instruments-Production Data