LM3S1G21 Datasheet, PDF (473/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
transitions are normally ½ the baud rate (COUNT0 = 1) because the EPI block forces data vs. control
to change on alternating clocks. When using dual chip selects, each chip select can access the bus
using differing baud rates by setting the CSBAUD bit in the EPIHBnCFG2 register. In this case, the
COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n transactions.
Additionally, the Host-Bus mode provides read and write wait states for the data portion to support
different classes of device. These wait states stretch the data period (hold the rising edge of data
strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS
bits in the EPI Host-Bus n Configuration (EPIHBnCFG) register.
10.4.2.4
Sub-Modes of Host Bus 8/16
The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four
cases. The four sub-modes are selected using the MODE bits in the EPIHBnCFG register, and are:
1. Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC
parts, and some ATmega parts. When used for standard SRAMs, a latch must be used between
the microcontroller and the SRAM. This sub-mode is provided for compatibility with existing
devices that support data transfers without a latch (that is, CPLDs). In general, the de-muxed
sub-mode should normally be used. The ALE configuration should be used in this mode, as all
Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an
external latch to capture the address then hold until the data phase. The ALE configuration is
controlled by configuring the CSCFG field to be 0x0 in the EPIHBnCFG2 register. The ALE can
be enhanced to access two external devices with two separate CSn signals. By configuring the
CSCFG field to be 0x3 in the EPIHBnCFG2 register, EPI0S30 functions as ALE, EPI0S27
functions as CS1n, and EPI0S26 functions as CS0n. The CSn is best used for Host-Bus
unmuxed mode, in which EPI address and data pins are separate. The CSn indicates when the
address and data phases of a read or write access are occurring.
2. Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB).
This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts.
This mode is generally used with real SRAMs, many EEPROMs, and many NOR Flash memory
devices. Note that there is no hardware command write support for Flash memory devices; this
mode should only be used for Flash memory devices programmed at manufacturing time. If a
Flash memory device must be written and does not support a direct programming model, the
command mechanism must be performed in software. The CSn configuration should be used
in this mode. The CSn signal indicates when the address and data phases of a read or write
access is occurring. The CSn configuration is controlled by configuring the CSCFG field to be
0x1 in the EPIHBnCFG2 register.
3. Continuous read mode where address and data are separate. This sub-mode is used for real
SRAMs which can be read more quickly by only changing the address (and not using RDn/OEn
strobing). In this sub-mode, reads are performed by keeping the read mode selected (output
enable is asserted) and then changing the address pins. The data pins are changed by the
SRAM after the address pins change. For example, to read data from address 0x100 and then
0x101, the EPI controller asserts the output-enable signal and then configures the address pins
to 0x100; the EPI controller then captures what is on the data pins and increments A0 to 1 (so
the address is now 0x101); the EPI controller then captures what is on the data pins. Note that
this mode consumes higher power because the SRAM must continuously drive the data pins.
This mode is not practical in HB16 mode for normal SRAMs because there are generally not
enough address bits available. Writes are not permitted in this mode.
4. FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external
XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios,
January 22, 2012
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