LM3S1G21 Datasheet, PDF (852/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Signal Tables
Table 19-3. Signals by Signal Name (continued)
Pin Name
U1RTS
U1Rx
U1Tx
U2Rx
U2Tx
VBAT
Pin Number Pin Mux / Pin
Assignment
43
PF6 (10)
61
PF1 (9)
10
PD0 (5)
12
PD2 (1)
23
PC6 (5)
26
PA0 (9)
66
PB0 (5)
92
PB4 (7)
11
PD1 (5)
13
PD3 (1)
22
PC7 (5)
27
PA1 (9)
67
PB1 (5)
91
PB5 (7)
10
PD0 (4)
19
PG0 (1)
92
PB4 (4)
98
PD5 (9)
6
PE4 (5)
11
PD1 (4)
18
PG1 (1)
99
PD6 (9)
55
fixed
Pin Type
O
I
O
I
O
-
VDD
VDDA
8
fixed
-
20
32
44
56
68
81
93
3
fixed
-
VDDC
VREFA
38
fixed
-
88
90
PB6
I
Buffer Type^a Description
TTL
UART module 1 Request to Send modem flow
control output line.
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
Power
Power
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
Positive supply for I/O and some logic.
Power
Power
Analog
The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 21-2 on page 894, regardless
of system implementation.
Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.3 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to the LDO pin and an external capacitor
as specified in Table 21-6 on page 899.
This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA
input is limited to the range specified in Table
21-26 on page 911 .
852
January 22, 2012
Texas Instruments-Production Data