LM3S1G21 Datasheet, PDF (629/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
Bit/Field
17
16
15:4
3
2
Name
DCINSS1
DCINSS0
reserved
IN3
IN2
Type
RO
RO
RO
R/W1C
R/W1C
Reset
0
0
0
0
0
Description
Digital Comparator Interrupt Status on SS1
Value Description
1 Both the INRDC bit in the ADCRIS register and the DCONSS1
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
Digital Comparator Interrupt Status on SS0
Value Description
1 Both the INRDC bit in the ADCRIS register and the DCONSS0
bit in the ADCIM register are set, providing a level-based
interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Interrupt Status and Clear
Value Description
1 Both the INR3 bit in the ADCRIS register and the MASK3 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register.
SS2 Interrupt Status and Clear
Value Description
1 Both the INR2 bit in the ADCRIS register and the MASK2 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit in the ADCRIS register.
January 22, 2012
629
Texas Instruments-Production Data