LM3S1G21 Datasheet, PDF (699/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
Bit/Field
6
5
4
3
2
Name
RXFF
TXFF
RXFE
BUSY
DCD
Type
RO
RO
RO
RO
RO
Reset
0
Description
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
0 The receiver can receive data.
0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
0 The transmitter is not full.
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
0 The receiver is not empty.
0
UART Busy
Value Description
1 The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
0 The UART is not busy.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
0
Data Carrier Detect
Value Description
1 The U1DCD signal is asserted.
0 The U1DCD signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
January 22, 2012
699
Texas Instruments-Production Data