LM3S1G21 Datasheet, PDF (604/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Analog-to-Digital Converter (ADC)
Table 13-1. ADC Signals (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
AIN6
98
PD5
I
Analog Analog-to-digital converter input 6.
AIN7
97
PD4
I
Analog Analog-to-digital converter input 7.
VREFA
90
PB6
I
Analog This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA
input is limited to the range specified in Table
21-26 on page 911 .
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 13-2. ADC Signals (108BGA)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
AIN0
B1
PE7
I
Analog Analog-to-digital converter input 0.
AIN1
A1
PE6
I
Analog Analog-to-digital converter input 1.
AIN2
B3
PE5
I
Analog Analog-to-digital converter input 2.
AIN3
B2
PE4
I
Analog Analog-to-digital converter input 3.
AIN4
A2
PD7
I
Analog Analog-to-digital converter input 4.
AIN5
A3
PD6
I
Analog Analog-to-digital converter input 5.
AIN6
C6
PD5
I
Analog Analog-to-digital converter input 6.
AIN7
B5
PD4
I
Analog Analog-to-digital converter input 7.
VREFA
A7
PB6
I
Analog This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA
input is limited to the range specified in Table
21-26 on page 911 .
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
The Stellaris ADC collects sample data by using a programmable sequence-based approach instead
of the traditional single or double-sampling approaches found on many ADC modules. Each sample
sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC
to collect data from multiple input sources without having to be re-configured or serviced by the
processor. The programming of each sample in the sample sequence includes parameters such as
the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence. In addition, the μDMA can be
used to more efficiently move data from the sample sequencers without CPU intervention.
13.3.1
Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 13-3 on page 605 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. Each sample that is captured is stored in the FIFO.
604
January 22, 2012
Texas Instruments-Production Data